Thursday January 03, 2019

The Future of Silicon Scaling

As we've said before, squeezing more performance out of denser silicon chips every few years is becoming a more difficult endeavor. Intel's 10nm process has been nothing but trouble so far, Globalfoundries dropped 7nm because it was too expensive, and TSMC (who are reportedly making AMD's upcoming 7nm chips) is dumping 10s of billions of dollars into research and manufacturing. This week, Semiconductor Engineering talked to several leading figures in the chipmaking and design industries, who had some interesting insights into the future of chip design. Among other things, the finFET transistors Intel pioneered will supposedly "run out of steam" beyond 5nm, meaning the industry will need to look at alternatives like nanosheet and nanowire FETs. Meanwhile, progress is reportedly being made in 3D stacking technology, advanced packaging technologies are becoming more cost effective, and other companies are looking and the possibility of performing some computation in system memory, instead of shuffling it over a high latency, power hungry bus to a different chip.

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"In the previous generations, the answer has been that transistor density and Moore's Law will play the lead role to solve computing problems," said Raja Koduri, senior vice president of Core and Visual Computing at Intel. "But as the process node transitions have slowed from the pace of the previous decades, it is the essence of Moore's Law that continues to provide new technologies and capabilities to meet the demands of modern computing. The message of Moore's Law is about more than transistors alone, with the combination of transistors, architectural research, connectivity advancements, faster memory systems, and software working together to drive it forward..."

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