Today's Hard|Forum Post
Today's Hard|Forum Post

Thursday December 06, 2018

MRAM Found to Outperform SRAM Cache at 5nm

As we've said before, Moore's law is slowing down and new nodes become less practical, so semiconductor companies and institutions are pouring more and more time and resources into alternative memory research. Magnetoresistive random access memory is one of the more promising alternatives, and new research suggests it can outperform SRAM in CPU caches on the upcoming 5nm node. This is the sort of cache you'd see marked as L1, L2, or L3 on a CPU spec sheet, and the research by IMEC suggests that MRAM can get the job done using less power and less die area, all while retaining data when the power goes out. MRAM's advantages are particularly pronounced in caches over about 5MB, as MRAM's standby power apparently scales much better with cache size than SRAM's. That means this technology would probably show up as L2 or L3 in high end processors before anything else.

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"For the first time, DTCO and silicon-verified models allowed us to conclude that the STT-MRAM energy becomes more efficient as compared to SRAM for high-density memory cells beyond 0.4Mbytes and 5Mbytes density for read and write operations, respectively. The comparison also reveals that the latency of the STT-MRAM is sufficient to meet the requirements of the last-level caches in the high-performance computing domain, which operate around 100MHz clock frequency," said Gouri Sankar Kar, program director at IMEC, in a statement. It should be considered that further improvements are expected to come with spin-orbit torque MRAMs now emerging from research and that show superior characteristics.

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