Intel Gives Larrabee Details, More To Come

While the bulk of detailed information on Intel’s Larrabee won’t be revealed for another week at SIGGRAPH 2008, the company did release a bit of information (contained in the pages and graphs below) today that will give you an idea of what you can expect when Intel takes the wraps off Larrabee next week.

The following is a quote from the paper linked in the documents above. Click the link for the complete article.

This paper presents a many-core visual computing architecture code named Larrabee, a new software rendering pipeline, a manycore programming model, and performance analysis for several applications. Larrabee uses multiple in-order x86 CPU cores that are augmented by a wide vector processor unit, as well as some fixed function logic blocks. This provides dramatically higher performance per watt and per unit of area than out-of-order CPUs on highly parallel workloads. It also greatly increases the flexibility and programmability of the architecture as compared to standard GPUs. A coherent on-die 2nd level cache allows efficient inter-processor communication and high-bandwidth local data access by CPU cores. Task scheduling is performed entirely with software in Larrabee, rather than in fixed function logic. The customizable software graphics rendering pipeline for this architecture uses binning in order to reduce required memory bandwidth, minimize lock contention, and increase opportunities for parallelism relative to standard GPUs. The Larrabee native programming model supports a variety of highly parallel applications that use irregular data structures. Performance analysis on those applications demonstrates Larrabee's potential for a broad range of parallel computation.

Intel also included a few helpful slides and graphs to give you a little more information about Larrabee’s architecture before the announcement on August 12th.

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