![[H]ardOCP](/images/blank.gif){kind=small}
- Date:
- Wednesday, June 24, 2009
- Author:
- Morry Teitelman
- Editor:
- Kyle Bennett
- Google +1
DFI UT X58-T3eH8
The UT X58-T3eH8 is DFI’s answer to the current onslaught of Intel X58 chipset based motherboards. The board is part of DFI’s much vaunted LanParty line of boards, squarely aimed at the gaming and hardware enthusiast. It looks to be strong contender in this highly competitive space.
BIOS
DFI chose to base the UT X58-T3eH8’s BIOS on the popular Phoenix AwardBIOS template. The BIOS used for testing and shown below is version 0217.
The Hard Disk Boot Priority submenu, accessed from the Advanced BIOS Features menu, shows determines the access order for all connected hard drive devices, including properly detected USB 2.0 type drives.
The Integrated Peripherals menu houses various submenus with options for controlling the various integrated and onboard system devices.
The OnChip IDE Device submenu contains configuration settings for both the ICH10R and JMicron SATA RAID controllers. The SATA Mode option controls the configuration for the ICH10R ports, with both standalone and RAID type settings available. Note that the Intel RAID boot BIOS will only show with drives connected to the onboard ICH10R’s SATA 2 ports. The LEGACY Mode Support setting restricts the ICH10R controller to using only a total of 4 SATA 2 devices when enabled. The operational state of the JMicron controller is set via the Onboard JMB363 option, with the JMicron RAID boot BIOS showing with the RAID+IDE setting selected.
The Onboard Device submenu contains settings for configuring the Marvell GigE LAN controllers, the IEEE 1394 controller, and the Realtek HD audio subsystem.
The USB Device Setting submenu contains USB related configuration settings, including those related to port speed mode. Device specific emulation settings show in this menu for all connected and active devices.
The PnP/ PCI Configurations menu contains the plug and play and PCI bus related configuration settings. While you are unable to directly assign IRQ interrupt settings, you can assign IRQ’s to a specific pool via the IRQ Resources submenu. Note that this submenu becomes user accessible with the Resources Controlled By option set to Manual.
The PC Health Status menu displays real-time statistics on BIOS monitored fan speeds, device temperatures, and device voltages. This menu also offers temperature based configuration for several of the onboard fan headers through the use of a minimum and maximum temperature threshold mechanism, as well as automated system shutdown based on system temperature.
The Genie BIOS Setting menu is a centralized location for accessing all overclocking related settings, presented in the top level menu itself and through a series of submenus. The settings housed in the top level menu have to do with the system bus speed settings only. The Turbo Mode Function option controls the ability to set the CPU ratio to a ratio higher than the default setting on a per core basis. The CPU Non-Turbo Clock Ratio setting controls the CPU multiplier setting with Turbo Mode disabled. Enabling the QPI Controls Settings and QPI Link Fast Mode options allows for user configuration of the QuickPath Interconnect bus speed using the QPI Frequency setting. This option allows for a maximum speed of 48x over the current base clock setting. The board’s base clock setting itself is configured via the CPU Base Clock(BCLK) option, with a maximum 250MHz bus speed selectable. The Boot Up CPU Base Clock option allows for configuration of a default base clock speed at system initialization time, also with a 250MHz maximum bus speed available. The PCIE Clock setting sets the PCI-Express bus speed independently from the base clock speed, also with a 250MHz maximum allowed speed. The DRAM Frequency option sets the board memory speed through a set of preconfigured multipliers with speed determined by the current base clock setting. The maximum speed multiplier for the DRAM available is 16x. Similarly, the UnCore Frequency setting controls the UnCore bus speed via base clock controlled multipliers with up to a 32x multiplier selectable.
The CPU Feature submenu contains all CPU specific configuration settings, including: CPU Thermal management, EIST support, C1E support, Execute Disable Bit, Intel virtualization technology, HyperThreading operation control, and core operational controls (Active Processing Cores).
The DRAM Timing submenu contains all memory timing related options including: Channel Interleave Setting; Bank Interleave Setting; local memory mapping (Memory LowGap); command rate; CAS latency; RAS to CAS delay; RAS precharge delay; active to precharge delay (RAS# Precharge (tRAS)); row refresh cycle delay (REF to ACT Delay(tRFC)); write recovery time (Write to PRE Delay(tWR)); write to read delay; RAS to RAS delay (ACT to ACT Delay(tRRD)); row cycle time; read to precharge delay; and four active window delay.
The Voltage Setting submenu contains all board voltage related settings. The CPU voltage is configured via the CPU VID Control option, with a 1.60V maximum. This voltage maximum can be increased using the CPU VID Special Add option, which can over volt the current CPU voltage setting by just under 115%. The system memory voltage, set through the DRAM Bus Voltage option, can be set to a 2.40V maximum. Note that due to the fact that the memory controller is internal for the Core i7 processors, using more than 1.65V could cause permanent internal damage to your costly processor. The DRAM PWM Switch Frequency and DRAM PWM Phase Control options configure the operation of the DRAM power regulation circuitry. The CPU Vtt voltage is configured with two settings, the CPU VTT Special Add and CPU VTT Voltage options. The CPU VTT Voltage option allows for a maximum setting of 1.61V, while the Add option allows for overvolting of the selected VTT base voltage by up to 0.1875V. The VTT PWM Switch Frequency and VTT PWM Phase Control settings configure the CPU Vtt related power regulation circuitry. The CPU power regulation circuitry voltage can be set to a maximum of 2.15V via the CPU PLL Voltage option. The Northbridge voltages are configured via the IOH/ICH 1.1V Voltage and the IOH Analog Voltage settings, with a 1.73V and 1.45V maximum allowed for each. The Southbridge voltage is similarly split between the ICH 1.5 Voltage and ICH 1.05V Voltages options, each with maximums of 2.1V and 1.35V respectively. The DRAM reference voltage can be set on a per channel basis from a -15.5% to a +15.5% of the base dram voltage setting.
The CMOS Reloaded menu allows for storage and retrieval of up to 4 individual full BIOS profiles. These profiles can be stored with up to a 4 line description and can be tied to an individual hotkey. Furthermore, the profiles can be accessed via the DFI ABS application and saved to a shareable profile via that tool.