![[H]ardOCP](/images/blank.gif){kind=small}
- Date:
- Tuesday , August 17, 2004
- Author:
- Morry Teitelman
- Editor:
- Kyle Bennett
- Google +1
ABIT AV8
ABIT chose to harness the power of the VIA K8T800Pro chipset for their AMD socket 939 motherboard. We find out whether this board is worthy of the ABIT moniker.
BIOS (continued)
The Advanced Chipset Features submenu contains a number of submenus for configuring chipset related functions, including memory and HyperTransport link timings. The VLink Data Rate option controls the speed of the Northbridge to Southbridge link, with the 8x setting being the more aggressive selection.
The DRAM Configuration submenu contains settings which control control all aspects of the memory bus operation.
Setting the DRAM Timing Selectable option to Manual allows for user configuration of all memory related settings. The DRAM Clock option controls the DRAM FSB by way of internal dividers, with ratios being DRAM FSB:CPU FSB: DDR200 is 1:2; DDR266 is 2:3; DDR333 is 5:6; and DDR400 is 1:1. The user has the ability to configure the following memory timing options: Command Rate; CAS latency; RAS to CAS delay; active to precharge time; RAS precharge delay; row cycle time; refresh row cycle time; RAS to RAS delay; write recovery time; write to read delay; and read to write delay. Note that on all memory timings listed, the numerically lower setting forces more aggressive memory operation.
The LDT & PCI Bus Control submenu contains various settings for controlling the speed and bandwidth of the HyperTransport bus, as well as some PCI bus related options.
The Upstream LDT Bus Width and Downstream LDT Bus Width options control the up and down bandwidth of the HyperTransport channel, with the 16 bit setting the preferred selection. The LDT Bus Frequency option controls the data rate of the HyperTransport link, using multipliers based on the default 200 MHz CPU FSB, with the maximum allowable speed to 1000 MHz using the 5x mulitplier. Note that the actual HyperTransport link speed will increase if the CPU FSB is increased above 200 MHz. The HT Stop Tristate option controls the HyperTransport response to a CRC type error, with the option of the bus working in a tristate mode. In the case of a CRC error, the LDT bus goes in to a floating state if tristate mode is enabled.
The Integrated Peripherals menu contains a number of submenus for configuring all onboard components, including the SATA, LAN, and USB ports. The ICH6R based SATA ports are configured through the SATA RAID ROM option within the Onchip IDE Device submenu. When this option is enabled, the boot up RAID BIOS becomes available, allowing for setup of RAID 0 and 1 hardware arrays. The Onboard PCI Device submenu contains configuration options for the non-chipset integrated items utilizing the PCI bus. The onboard VIA Gigabit Ethernet controller can be configured using the Onboard LAN Controller option within this menu. The USB Emulation option controls the detection state of attached USB devices. If this option is set to OFF, then attached USB storage devices will not be detected at system initialization and cannot be used as system boot devices.
When a USB device is attached to the system at boot time and is properly detected by the system, it will show in the pull down device menu within the Hard Disk Boot Priority submenu selectable from within the Advanced BIOS Features menu.