![[H]ardOCP](/images/blank.gif){kind=small}
- Date:
- Sunday , November 02, 2003
- Author:
- Morry Teitelman
- Editor:
- Kyle Bennett
- Google +1
ABIT KV8-MAX3
As ABIT’s flagship AMD board, the KV8-MAX3 combines the VIA K8T800 chipset with ABIT’s own OTES and uGuru technologies. This MAX series board serves up support for AMD's Athlon64 754-pin CPU.
BIOS
The KV8-MAX’s BIOS is implemented around the Phoenix AwardBIOS. ABIT has heavily enhanced to the BIOS to make it more appealing to the enthusiast crowd.
The SoftMenu Setup page is ABIT’s trademark BIOS enhancement. Through this single page, you are able to manipulate the various board FSBs and voltages.
Setting the CPU Operating Speed option to User Define enables the CPU FSB Clock(MHz) option for user manipulation. This single setting controls all system FSBs, including the CPU, PCI, AGP, and HyperTransport FSBs. In its current revision, the K8T800 chipset does not support asynchronous CPU/HT/AGP/PCI FSB settings, instead using a preset divider method. The dividers available according to the ABIT BIOS are as follows (CPU:AGP:PCI): 1:6 (200:66:33); 1:7 (233:66:33); and 1:8 (266:66:33). With the CPU FSB Clock(MHz) option set to an FSB of 300, both the AGP and PCI were well out of spec since the 1:8 divider was in effect according to the ABIT BIOS.
When the Voltages Control option is set to User Define, all voltage options become user configurable. The CPU Core Voltage option controls how much voltage is fed to the CPU in increments of 1 mV. The maximum setting is 350mV, which set the CPU voltage at 1.85v. The AGP VDDQ Voltage controls the board AGP voltage, with a not so shabby maximum of 2.65v. This voltage should be sufficient to overcome any AGP bus related overclocking issues. The DDR Voltage option controls the amount of power going to your RAM, with an unbelievably high upper limit of 3.20v. It is recommended that an active cooling source, such as a system fan, blow on to your RAM when using anything above 2.9v. The HyperTransport Voltage option controls the voltage supplied to the HyperTransport channels between the CPU and the system. The maximum settable voltage of 1.40v should be sufficient for any overclock.
The Advance Chipset Features menu contains a series of submenus for controlling the behavior of the system memory, AGP bus, PCI bus, and HyperTransport bus. From the main screen, you have the option of modifying the data transfer rate between the VIA Northbridge and Southbridge controller using the VLink Data Rate option. Unless system stability is an issue, it is recommended to set this option to 8x for higher performance.
The DRAM Configuration submenu contains various options for setting the speed and aggressiveness of the system memory. With the DRAM Timing Selectable option set to Manual, all memory speed and timing related options become user configurable.
The DRAM Clock option configures the memory speed based on predefined dividers based on the CPU FSB. The dividers are broken down as follows (CPU:DDR): DDR200 (2:1); DDR266 (3:2); DDR333 (6:5); and DDR400 (1:1). The following memory timing options are available for configuration, with the lower number being the more aggressive setting: CAS latency; row cycle time; row refresh cycle time; RAS to CAS delay; RAS to RAS delay; RAS active time; RAS precharge time; write recover time; write to read delay; and read to write delay.
The LDT & PCI Bus Control submenu contains various options for configuring the HyperTransport channels between the CPU and the system as well as the system PCI bus.
The Upstream LDT Bus Width option controls the bandwidth for data moving from the system to the CPU, while the Downstream LDT Bus Width option controls the bandwidth available for data movement from the CPU to the system. In both cases, the 16 bit setting will give better overall system performance. The LDT Bus Frequency option configures the speed at which data transfers along the HyperTransport channels. The physical link speed is determined by the CPU FSB setting and the frequency multiplier selected. The multipliers available corresponding to the selected frequency setting are as follows: 200 (1x); 400 (2x); 600 (3x); and 800 (4x). Unless system stability becomes an issue, this setting should be set to 800 MHz for best overall system performance.
The Integrated Peripherals menu contains various options and submenus for controlling the board’s integrated peripherals. The VIA VT8237 SATA controller is configured using the SATA RAID ROM option within the OnChip IDE Device submenu. With this option enabled, the VT8237 RAID BIOS becomes accessible at boot time. Otherwise, no hardware RAID configuration is possible for drives connected to the VT8237 based SATA 150 ports. The Silicon Image controller is enabled through the Onboard RAID Controller option within the OnChip PCI Device submenu. With this option enabled, the Silicon Image RAID BIOS becomes accessible during system boot allowing for setup of hardware based RAID arrays.