![[H]ardOCP](/images/blank.gif){kind=small}
- Date:
- Monday , September 01, 2003
- Author:
- Morry Teitelman
- Editor:
- Kyle Bennett
- Google +1
ABIT IC7-MAX3
The IC7-MAX3 is ABITs attempt to perfect an already superior board, the IC7-G, through the optimizations and the addition of its much touted OTES technology.
BIOS
ABIT chose to stay with the familiar Phoenix AwardBIOS layout for the IC7-MAX3. In fact, the BIOS itself is almost identical to that of the IC7-G on which the board is based. There are, however, a few differences. Additions that ABIT knew the enthusiast crowd would love.
Note that all BIOS screen shots herein were taken with BIOS v1.1 loaded. However, all menus and options available with the new v1.2 BIOS remain unchanged from the v1.1 menus and options.
ABITs SoftMenu interface sets the standard for the jumper free overclockable BIOS. ABIT uses this technology to centralize all CPU and FSB related overclocking features, from MHz determination to component voltage settings. The end user is thus in full control of his/her chips overclocking destiny.
The very first option, CPU Operating Speed, determines the physical speed and multiplier settings of your CPU and various component FSBs automatically or manually. The various FSB and CPU speed related options become user accessible once the CPU Operating Speed option is set to User Defined. The CPU FSB can be customized through the Ext. Clock (CPU/AGP/PCI) option, from a minimum of 100 MHz all the way up to a possible 412 MHz maximum. The number selected will affect the system memory, AGP, and PCI bus speeds when combined with the options below it in the menu. The AGP Ratio (CPU:AGP:PCI) option contains multiple ways of setting the AGP and PCI bus FSBs through an automatically determined ratio, a divider setting up to x/8, and the ability to lock the buses at a set speed. When the AGP Ratio option is set to Fixed, the Fixed AGP/PCI Frequency option becomes accessible, allowing setting of the AGP bus speed from 66 MHz to a maximum of 96 MHz. The PCI bus speed is automatically set to half the speed of the selected AGP FSB.
The N/B Strap CPU As and DRAM Ratio (CPU:DRAM) options are used in conjunction with one another to determine the memory speed based on the CPU FSB selected through the Ext. Clock (CPU/AGP/PCI) option. In practice, it has been found that the N/B Strap CPU As option only takes effect when the setting selected is equal to or below the current CPU FSB. If the N/B Strap CPU As option is set to a higher setting than the current CPU FSB, the setting is ignored by the system, and the RAM will run as determined by the SPD settings. The following charts goes through the divider options available through the DRAM Ratio option with each of the various N/B Strap CPU As options selected.
N/B Strap CPU As | DRAM Ratio (CPU:DRAM) |
By CPU | 1:1 (533, 800 MHz CPUs) |
3:2 (800 MHz CPU) | |
3:4 (400 MHz CPU) | |
4:5 (533 MHz CPU) | |
5:4 (800 MHz CPU) | |
By SPD (DDR speed determined by internal memory circuitry) | |
PSB400 | 3:4 |
By SPD (DDR speed determined by internal memory circuitry) | |
PSB533 | 1:1 |
4:5 | |
By SPD (DDR speed determined by internal memory circuitry) | |
PSB667 | 1:1 |
5:4 | |
By SPD (DDR speed determined by internal memory circuitry) | |
PSB800 | 1:1 |
3:2 | |
5:4 | |
By SPD (DDR speed determined by internal memory circuitry) |
The system voltage settings are located in the lower section of the SoftMenu screen. The CPU Core Voltage option becomes user settable once the CPU Power Supply option is set to User Define. The CPU voltage itself can be set to a maximum of 1.90v, stepwise from 1.50v in a .025v progression. The DDR SDRAM Voltage option configures the voltage supplied to your power-starved memory, allowing up to a maximum of an impressive 3.2v. With this much voltage under user control, the overclocking possibilities are immense. Just keep in mind that the higher you set your memory voltage, the hotter the memory temperature will become. It wouldnt be a bad idea to place a fan over the memory for better air circulation. The AGP Voltage option is the last settable option on the page. This option allows for setting of the voltage going to your AGP card as high as 1.65v. Not a bad amount of voltage, but given the spectacular options available to the CPU and memory voltage wise, so meager a setting is a bit disappointing.
The Advanced Chipset Features menu contains options for controlling most chipset functions, from AGP settings to memory and system timing options. Changing the memory timings can lead to vast system performance increases over un-optimized settings.
By setting the DRAM Timing Selectable option to Manual, the user enables interaction with the four memory timing options. Memory settings available include CAS latency, Active to Precharge delay, RAS to CAS delay, and RAS Precharge delay. On all memory timing settings, setting a lower number causes the system memory to run in a more aggressive manner.
At the very bottom of the Advanced Chipset Features menu are the most interesting and talked about chipset optimization options. Known simply as Game Accelerator, this technology allows enhanced performance in a multi-tier manner through the preset options of Turbo, Street Racer, or F1, or through the Auto selection. Auto allows for user configuration of the Game Accelerator related options. The Game Accelerator technology was first introduced by ABIT as a method of squeezing i875P-like performance out of an i865PE chipset board. When coupled with a true i875P based board, these options make the boards performance just about untouchable. Note that the Street Racer and F1 options cause the chipset and memory to run extremely aggressively, leading in turn to severe memory related stability issues. The Refresh Cycle Time option determines how often the data contained in the memory modules is refreshed by the system; the more aggressive the setting, the faster the refresh time becomes. The Read Delay(tRD) and Read Delay Adjust(tRDA) options control how aggressively the memory is accessed for Read operations by setting the wait state between successive memory Reads to the selected setting within the Read Delay(tRD) option. The Command Per Clock(CPC) option determines the delay time between address commands based on the DRAM strobe clock.