Date:
Tuesday , July 16, 2002
Author:
Kyle Bennett
Editor:
Sean Quinn
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nForce2 Technology Preview

NVIDIA's new AMD Athlon mainboard chipset (codenamed Crush18) is promised to deliver killer performance as well as be the ultimate in integration.

continued...

nForce2 Northbridge Features (cont.)

Now that we've covered the single difference between the SPP and the IGP, let's have a look at what's common to both of them.

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Don't expect to see the above logo anywhere. I just took the two NVIDIA logos and bastardized them into a single graphic, because I think it better represents what you're going to get. NVIDIA's "TwinBank" memory controller is back. Their dual channel DDR controller is all grown up now and waiting to be paired with DDR400 memory. What you have is effectively a 128-bit memory subsystem which is theoretically capable of delivering 6.4GB/second of memory bandwidth when used with 400MHz DDR RAM. That's a lot of bandwidth for the AthlonXP platform.

If DDR400 turns you off from a cost standpoint, as it's very expensive at the moment, have no fear because the nForce2 is all about backwards compatibility. It will have no problem accepting your DDR266 or DDR333 RAM in matched pairs.

Although we haven't seen any hard numbers, NVIDIA is claiming greatly decreased latencies with their dual channel system, up to 50% less. I'm assuming this is a comparison with a basic single channel DDR memory system. An example of decreased latencies would be when the stick of RAM on controller A is being written to, the stick on controller B could be prepared for its next function. When it's time for that read or write to take place, there's "no" waiting, or latency involved. Here's what NVIDIA has to say about it.

Highest Memory Bandwidth – Tuned for System Performance

DualDDR combines the power of DDR400 to two independent intelligent memory controllers. This combination yields a staggering 6.4GB/sec. of memory bandwidth, twice the memory bandwidth of other DDR400 chipsets. 6.4GB/sec. of memory bandwidth yields higher system and graphics performance, resulting in more overall productivity.

More than just 6.4GB/sec. of raw memory bandwidth, DualDDR has been tuned specifically for better system performance on the nForce2 SPP (System Platform Processor). The nForce2 SPP clock sources for CPU, DRAM and AGP are truly asynchronous. With this decoupled clocking architecture, completions of reads or writes by the CPU are not dependent upon the completion of DRAM access or AGP access. Instead, intelligent arbitration and ordering logic ensures that data ordering integrity is maintained. The end result is the CPU must not unnecessarily wait for the memory subsystem, AGP, or the Media Communications Processor (MCP) to complete its tasks, in order to begin the next access.

This all sounds great, but I've yet to talk to any other chipset company that doesn't see the 133MHz AthlonXP CPU bus as a monolithic bottleneck right now. Keeping in mind that NVIDIA may be doing things differently, maybe they'll show the rest of the world the light. We brought this issue up with NVIDIA and they told us that the 133MHz bus speed wouldn't be holding them back as the bandwidth would be utilized elsewhere. They specifically mentioned 8X AGP performance. When asked for the tools to back up that statement, NVIDIA committed to looking into it. At the present time, however, they have not given us any tangible to work with. As usual, the benchmarks will tell all.

Back again is Dynamic Adaptive Speculative Processor, or DASP. It's certainly one of the features that got us hot and bothered with the nForce last year and one we never saw really amount to anything measurable. Here's a quote from our original DASP summation.

"NVIDIA "just" installed an L3 cache on the chipset. Ok, that is not right, but that is a good way of looking at it. The DASP watches what the CPU does as it accesses the memory and remembers what information it is accessing it for. The DASP has the ability to store 8 possible solutions that the CPU MIGHT need. When it sees the CPU asking for a specific instruction that it has stored, it heads that request off at the pass so to speak. Instead of the CPU having to go all the way out to the memory and back, the DASP can shorten its trip by half by supplying what it is looking for. See why I say it is a sort of L3 cache now?

NVIDIA will call it a multi-datapath prediction/prefetching technology that can track multiple unrelated streams of data requests and employs a proprietary selection process to select candidate cache lines to read into an on-die cache, but I think they were just trying to make it sound important.

OK, two key words here so far: "on-die cache" and "proprietary". Well I guess technically that is three or four, but who is counting. Keep in your mind that the IGP gives the CPU a "third cache" (that is our way of looking at it) much like the cache of yesteryear that was on the mainboard. Since this is proprietary and in the process of being patented by NVIDIA it is not going to be showing up on other mainboards in this exact form. I am sure we will see some variations on it though."

In the past NVIDIA made claims of a 20% increase associated with DASP that never showed out in our testing. They haven't made those claims this time and were fairly ambiguous about it except to say that DASP was now into its second generation. A much more aggressive DASP algorithm seems to be used with the nForce2. We're told that DASP has the ability to utilize an idle bus for instruction prediction as well, but we have yet to see the white paper on that.

As many of your know, SiS is currently producing a chipset that's 8X AGP compliant. Many of you may also know that the new R300 and NV28 chipsets are 8X AGP compliant as well. The nForce2 will take advantage of 8X AGP technology. Excitingly enough, the on-chip IGP will also use 8X AGP transfers. 8X AGP allows for just over 2GB/sec of data to move across the bus at its maximum theoretical limit.

HyperTransport is here again as well. It allows for 800MB/second transfer rates between the northbridge and southbridge. While this doesn't really come into play in our northbridge discussion, we'll look at what it could mean to us when talking about the southbridge.

nForce2 Northbridge Summation:

The new northbridges we're seeing here can be summed up fairly quickly as a simple evolutionary step from the original nForce. The on-chip GPU is now a variation of the GeForce4 MX and is only implemented on the "IGP". Outside of that, the IGP and SPP share the same features. Dual Channel DDR is present, supporting speeds of 266MHz, 333MHz, and 400MHz DDR. DASP has been modified somewhat to do a better job predicting what information will be needed in its cache. The northbridge will support 8X AGP transfers and will be connected to the southbridge (coined the MCP by NVIDIA) via a HyperTransport bus allowing for 800MB/sec of data transfer.

The IGP GeForce4 MX integrated graphics solution will have all the benefits of the add-in card carrying the GF4 MX chipset. You can read up on those features in our GeForce4 Tech Article. How exactly nView dual monitor setup will be implemented on the board level is not yet known to me. NVIDIA has stressed, however, that the nForce2 IGP does have two CRT controllers, enabling the use of nView with no AGP cards present.